Circuitos Digitales - Programación VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity UART_Receiver is

    Port (

        CLK         : in  STD_LOGIC;

        Rx          : in  STD_LOGIC; -- Línea de recepción serie

        Rx_Rdy      : out STD_LOGIC; -- Listo para leer

        Data        : out STD_LOGIC_VECTOR(7 downto 0); -- Dato recibido

        Error       : out STD_LOGIC; -- Error

        CLR_Error   : in  STD_LOGIC; -- Borrar error

        Rd          : in  STD_LOGIC  -- Leer dato

    );

end UART_Receiver;

architecture Behavioral of UART_Receiver is

    signal Rx_Shift_Register : STD_LOGIC_VECTOR(8 downto 0) := (others => '1'); -- Registro de cambio para recibir datos

    signal Bit_Counter       : INTEGER := 0; -- Contador de bits recibidos

    signal Parity_Bit        : STD_LOGIC := '0'; -- Bit de paridad recibido

    signal Parity_Error      : STD_LOGIC := '0'; -- Error de paridad

begin

    process(CLK)

    begin

        if rising_edge(CLK) then

            -- Reset de error cuando se activa CLR_Error

            if CLR_Error = '1' then

                Error <= '0';

            end if;

            -- Detectar el inicio de la recepción

            if Rx = '0' and Rx_Shift_Register(8) = '1' then

                Bit_Counter <= 0;

            end if;

            -- Contar bits y almacenar en el registro

            if Bit_Counter > 0 and Bit_Counter <= 8 then

                Rx_Shift_Register(Bit_Counter) <= Rx;

                Bit_Counter <= Bit_Counter + 1;

            end if;

            -- Recibir bit de paridad

            if Bit_Counter = 9 then

                Parity_Bit <= Rx;

                Bit_Counter <= Bit_Counter + 1;

            end if;

            -- Recibir bit de stop y verificar paridad

            if Bit_Counter = 10 then

                if Rx = '1' then

                    -- Verificar paridad

                    if Parity_Bit /= Parity_Bit_XOR then

                        Parity_Error <= '1';

                        Error <= '1';

                    end if;

                    -- Asignar datos a la salida

                    Data <= Rx_Shift_Register(7 downto 0);

                    Rx_Rdy <= '1';

                else

                    Error <= '1';

                end if;

                -- Resetear registros

                Rx_Shift_Register <= (others => '1');

                Bit_Counter <= 0;

                Parity_Bit <= '0';

            else

                Rx_Rdy <= '0';

            end if;

        end if;

    end process;

end Behavioral;